Digital circuitry frequently includes circuitry for latching information. Commonly, such latching circuitry latches information input from a data input node and from a scan input node. The data input node and the scan input node are multiplexed to the latching circuitry, so the latching circuitry inputs information from no more than one of the data input node and the scan input node at any particular moment.
The data input node is connected to one or more functional units of the digital circuitry, consistent with the digital circuitry's primary functional purpose. By comparison, the scan input node is connected to one or more scan inputs of the digital circuitry, consistent with serial scan testing techniques. During normal operation of the digital circuitry, the latching circuitry latches a logic state of the data input node. During testing of the digital circuitry according to serial scan testing techniques, the latching circuitry is able to latch a logic state of the scan input node.
By latching the logic state of the scan input node instead of the data input node, the latching circuitry is more readily initialized to a predetermined logic state for testing purposes. This is because the latching circuitry bypasses one or more functional units (connected to the data input node) by latching logic states of the scan input node instead of the data input node. Nevertheless, parasitic capacitance results from the scan input node and its connected scan input circuitry. With typical previous techniques, this parasitic capacitance results in a speed penalty during normal operation of the digital circuitry where the latching circuitry latches information input from the data input node.
Thus, a need has arisen for a method and circuitry for latching information, in which parasitic capacitance (resulting from a scan input node and its connected scan input circuitry) results in less (relative to typical previous techniques) of a speed penalty during normal operation where latching circuitry latches information input from a data input node.